This invention relates to fabrication of bubble memory chip devices. In particular, this invention relates to the production of the fine conductor pattern on the garnet substrate prior to the addition of further permalloy and dielectric elements.
Conventional bubble memory circuits are fabricated in a non-planar process in which the permalloy elements cross over the conductor elements in the active areas of the chip. These non-planar devices are usually limited in performance by weak margins or limits of performance in the areas where step coverage of conductors by permalloy elements exists. One solution to this problem of marginal performance would be a process in which the permalloy elements are fabricated on a planar surface having buried conductors therein. It is one of the objects of this invention to produce a bubble memory chip and method for fabrication which would have buried conductors on which permalloy elements would be fabricated. Among the advantages of such an arrangement would be the linear flux continuity of the permalloy elements. Because there would be no discontinuities at the steps of the permalloy elements there is a reduced need for drive and power requirements and a corresponding increase in production yield and operating margin characteristics. Also, all portions of each permalloy element would be spaced at the uniform optimum distance from the garnet substrate thereby reducing error rates and increasing performance margins. A further advantage would be obtained in the fabrication steps involving the permalloy elements because a higher resolution and greater density could be obtained in these elements without the step features. Also, the proper formation of steps in conductive elements requires careful control of the edges at the step to provide proper conductor thickness and conductivity. By eliminating steps the conductor conductivity would be optimized. Similarly, the planar conductors uniformly encased in the dielectric media would result in more uniform magnetic fields than those achieved using step features.
Several planar processes have been developed for semiconductor devices. These processes involve the so called lift-off techniques in which either the conductor or dielectric is back filled to bring the surface to a planar level. However the materials used in semiconductor manufacture are not appropriate for bubble memory device manufacture because the materials used in the lift-off process are dielectric rather than conductive and because of the comparatively different surface features in the bubble memory design.
An excellent paper discussing this subject is that by J. P. Reecksten and R. Kowalchuk found in IEEE Transactions on Magnetics, Volume MAG-9, Number 3, September 1973, entitled "Fabrication of Large Bubble Circuits" at page 465. The various processes described suffer from a variety of problems. Stencil deposition requires either double masking or metal/resist lift-off. The fine geometry and unique topography of bubble circuits makes this difficult to implement. Dielectric lift-off is not compatible with the high temperature deposition techniques used in bubble memory fabrication. Electroless stencil techniques demand thin, buried, catalytic layers or an additional masking step requiring close registration. All techniques requiring more than a single registration process step becomes significantly more complicated because the various registration layers have to be aligned with one another as well as features involved. The invention described in the present application is a development based on the stencil etch technique.